1. Field of the Invention
The invention disclosed and claimed herein generally pertains to a method for automatically validating or verifying manufacturing test rules that pertain to integrated circuits or other electronic components. More particularly, the invention is directed to a method of the above type pertaining to rules for components that contain analog and/or custom digital circuits, as well as purely digital logic circuits. Even more particularly, the invention is directed to a method of the above type wherein test cases used in the method each have a stimulus that comprises one or more multiple input vectors.
2. Description of the Related Art
Manufacturing test rules are very necessary in designing integrated circuits, blocks of logic or other electronic components. A manufacturing test rule generally indicates the logical representation of an electronic component from a manufacturing test perspective. This rule describes all possible valid outputs of a component, for each possible pattern or combination of valid inputs, and is needed in order to measure testability. Manufacturing test rules are also needed to determine the locations of any manufacturing defects.
Many manufacturing test rules are created by hand, and are thus very prone to error. Because of this, and also because of the importance of such rules, it is essential to validate their accuracy or correctness. For example, care must be taken to ensure that the test rule representation of a logic block matches the way in which the block actually operates during test mode. This requirement becomes increasingly important in high-speed applications, where a growing number of low-level components are being designed with analog or custom digital logic, in order to enhance speed and functionality. At present, there is no automatic method to create rules for these types of components, so the rules must be created manually. Accordingly, validating the rules for these types of components is of paramount importance. Manufacturing test rules for digital logic blocks, while somewhat easier to generate than manufacturing test rules for analog or custom digital logic, also require validation to ensure their integrity and testability.
Notwithstanding the importance of validating manufacturing test rules, currently available techniques for performing this task are largely manual, and are mainly done in connection with a top-level rule (i.e., a manufacturing test rule for a top-level core, that contains many other manufacturing test rules). Working with a top-level rule may reduce the number of verification environments that must be created. However, with this approach it may be difficult to pinpoint where the failure in a test rule occurs. This approach can also increase both the simulation time, due to the size of the rule, and the state space of the input vectors in the simulator.